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numicro? nuc100 product brief arm cortex?-m0 32-bit microcontroller publication release date: may 6, 2011 - 1 - revision v2.01 numicro? family nuc100 product brief the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation.
numicro? nuc100 product brief publication release date: may 6, 2011 - 2 - revision v2.01 contents 1 general des cription ......................................................................................................... 6 2 features ....................................................................................................................... .......... 7 2.1 numicro ? nuc100 features ? advanc ed line.............................................................. 7 3 parts information list and pin conf iguration .................................................... 11 3.1 numicro ? nuc100 products selection guide ............................................................. 11 3.1.1 numicro ? nuc100 medium density adva nce line sele ction guide ............................. 11 3.1.2 numicro ? nuc100 low density advanc e line select ion guide ................................... 11 3.2 pin config uration .......................................................................................................... 13 3.2.1 numicro ? nuc100 medium d ensity pin diagr am ......................................................... 13 3.2.2 numicro ? nuc100 low densit y pin diagram ............................................................... 16 3.3 pin descr iption.............................................................................................................. 18 3.3.1 numicro ? nuc100 medium dens ity pin de scription ..................................................... 18 3.3.2 numicro ? nuc100 low densit y pin descr iption ........................................................... 25 4 block diagram .................................................................................................................. .. 30 4.1 numicro ? nuc100 medium dens ity block diagram ................................................... 30 4.2 numicro ? nuc100 low densit y block diagram.......................................................... 31 5 electrical cha racteristics......................................................................................... 31 5.1 absolute maxi mum ratings .......................................................................................... 31 5.2 dc electrical characteristics ........................................................................................ 33 5.2.1 numicro ? nuc100/nuc120 medium density dc electrical characte ristics ................. 33 5.2.2 numicro ? nuc100/nuc120 low density dc el ectrical char acteristics ....................... 38 5.2.3 operating current curve (t est condition : run nop)....................................................... 42 5.2.4 idle current curve .......................................................................................................... 44 5.2.5 power down current curve............................................................................................ 46 5.3 ac electrical ch aracteristics ........................................................................................ 47 5.3.1 external 4~24 mhz high speed crystal ......................................................................... 47 5.3.2 external 32.768 khz low speed crystal ........................................................................ 48 5.3.3 internal 22.1184 mhz high speed o scillator.................................................................. 48 5.3.4 internal 10 khz lo w speed o scillato r............................................................................. 48 5.4 analog characteristics.................................................................................................. 49 5.4.1 specification of 12-bit saradc ..................................................................................... 49 5.4.2 specification of ldo & power m anagement .................................................................. 50 5.4.3 specification of lo w voltage reset ................................................................................ 51 5.4.4 specification of br own-out detector............................................................................... 51 5.4.5 specification of po wer-on rese t (5 v) ........................................................................... 51 5.4.6 specification of te mperature sens or ............................................................................. 52 5.4.7 specification of compar ator ........................................................................................... 52 5.4.8 specification of usb phy .............................................................................................. 53 5.5 spi dynamic characteristics ........................................................................................ 54 6 package dime nsio ns ......................................................................................................... 56
numicro? nuc100 product brief publication release date: may 6, 2011 - 3 - revision v2.01 6.1 100l lqfp (14x14x1.4 mm footprin t 2.0mm) .............................................................. 56 6.2 64l lqfp (10x10x1.4mm footprint 2.0 mm) ................................................................ 57 6.3 48l lqfp (7x7x1.4mm footprint 2.0mm) ..................................................................... 58 7 revision histor y ............................................................................................................... . 59
numicro? nuc100 product brief publication release date: may 6, 2011 - 4 - revision v2.01 figures figure 3-1 numicro ? nuc100 series selecti on code ................................................................... 12 figure 3-2 numicro ? nuc100 medium density lqfp 100-pin pin diagram ............................... 13 figure 3-3 numicro ? nuc100 medium density lq fp 64-pin pi n diagram ................................. 14 figure 3-4 numicro ? nuc100 medium density lq fp 48-pin pi n diagram ................................. 15 figure 3-5 numicro ? nuc100 low density lqfp 64-pin pin diagram........................................ 16 figure 3-6 numicro ? nuc100 low density lqfp 48-pin pin diagram........................................ 17 figure 4-1 numicro ? nuc100 medium dens ity block diagram ................................................... 30 figure 4-2 numicro ? nuc100 low densit y block di agram ......................................................... 31 figure 7-1 typical crysta l applicatio n circuit ................................................................................ 47 figure 7.5-1 spi master dynam ic characteristics timing................................................................ 55 figure 7.5-2 spi slave dynamic characteristics timing.................................................................. 55
numicro? nuc100 product brief publication release date: may 6, 2011 - 5 - revision v2.01 tables table 1-1 connectivit y supported table......................................................................................... . 6
numicro? nuc100 product brief publication release date: may 6, 2011 - 6 - revision v2.01 1 general description the numicro ? nuc100 series is 32-bit microcontrollers with embedded arm ? cortex?-m0 core for industrial control and applications which need rich communication interfaces. the cortex?-m0 is the newest arm ? embedded processor with 32-bit performance and at a cost equivalent to traditional 8-bit microcontroller. numicro ? nuc100 series includes nuc100, nuc120, nuc130 and nuc140 product line. the numicro ? nuc100 advanced line embeds cortex?- m0 core running up to 50 mhz with 32k/64k/128k-byte embedded flash, 4k/8k/16k -byte embedded sram, and 4k-byte loader rom for the isp. it also equips with plenty of peripheral devices, such as timers, watchdog timer, rtc, pdma, uart, spi, i 2 c, i 2 s, pwm timer, gpio, ps/2, 12-bit adc, analog comparator, low voltage reset controller and brown-out detector. product line uart spi i 2 c usb lin can ps/2 i 2 s nuc100 nuc120 nuc130 nuc140 table 1-1 connectivity supported table
numicro? nuc100 product brief publication release date: may 6, 2011 - 7 - revision v2.01 2 features the equipped features are dependent on the product line and their sub products. 2.1 numicro ? nuc100 features ? advanced line ? core C arm ? cortex?-m0 core runs up to 50 mhz C one 24-bit system timer C supports low power sleep mode C single-cycle 32-bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4-levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? build-in ldo for wide operating voltage ranges from 2.5 v to 5.5 v ? flash memory C 32k/64k/128k bytes flash for program code (128kb only support in numicro ? nuc100/nuc120 medium density) C 4kb flash for isp loader C support in-system program (isp) application code update C 512 byte page erase for flash C configurable data flash address and size for 128kb system, fixed 4kb data flash for the 32kb and 64kb system C support 2 wire icp update through swd/ice interface C support fast parallel programming mode by external programmer ? sram memory C 4k/8k/16k bytes embedded sram (16kb only support in numicro ? nuc100/nuc120 medium density) C support pdma mode ? pdma (peripheral dma) C support 9 channels pdma for automatic dat a transfer between sram and peripherals (only support 1 channel in numicro ? nuc100/nuc120 low density) ? clock control C flexible selection for different applications C build-in 22.1184 mhz high speed oscillator (t rimmed to 1%) for system operation, and low power 10 khz low speed oscillator for watchdog and wake-up operation C support one pll, up to 50 mhz, for high performance system operation C external 4~24 mhz high speed crystal input for precise timing operation C external 32.768 khz low speed crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi bi-direction ? push-pull output ? open-drain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin can be configured as interr upt source with edge/level setting C high driver and high sink io mode support
numicro? nuc100 product brief publication release date: may 6, 2011 - 8 - revision v2.01 ? timer C support 4 sets of 32-bit timers with 24-b it up-timer and one 8-bit pre-scale counter C independent clock source for each timer C provides one-shot, periodic, toggle and continuous counting operation modes (numicro ? nuc100/nuc120 medium density only support one-shot and periodic mode) C support event counting function ( numicro ? nuc100/nuc120 low density only ) ? watchdog timer C multiple clock sources C 8 selectable time out period from 1.6ms ~ 26.0sec (depends on clock source) C wdt can wake-up from power down or idle mode C interrupt or reset select able on watchdog time-out ? rtc C support software compensation by setting frequency compensate register (fcr) C support rtc counter (second, minute, hour ) and calendar counter (day, month, year) C support alarm registers (second, minute, hour, day, month, year) C selectable 12-hour or 24-hour mode C automatic leap year recognition C support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C support wake-up function ? pwm/capture C built-in up to four 16-bit pwm generator s provide eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one dead-zone generator for complementary paired pwm C up to eight 16-bit digital capture timers (shared with pwm timers) provide eight rising/falling capture inputs C support capture interrupt ? uart C up to three uart controllers (numicro ? nuc100/nuc120 low density only support 2 uart controllers) C uart ports with flow control (txd, rxd, cts and rts) C uart0 with 63-byte fifo is for high speed C uart1/2(optional) with 15-byte fifo for standard device C support irda (sir) function C support rs-485 9-bit mode and direction control. (numicro ? nuc100/nuc120 low density only) C programmable baud-rate generator up to 1/16 system clock C support pdma mode ? spi C up to four sets of spi controlle r (numicro ? nuc100/nuc120 low density only support 2 spi controllers) C master up to 20 mhz, and slave up to 10 mhz (chip working @ 5v) C support spi master/slave mode C full duplex synchronous serial data transfer C variable length of transfer data from 1 to 32 bits C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently
numicro? nuc100 product brief publication release date: may 6, 2011 - 9 - revision v2.01 C 2 slave/device select lines when it is as the master, and 1 slave/device select line when it is as the slave C support byte suspend mode in 32-bit transmission C support pdma mode ? i 2 c C up to two sets of i 2 c device C master/slave mode C bidirectional data transfer between masters and slaves C multi-master bus (no central master) C arbitration between simultaneously transmitti ng masters without co rruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow versatile rate control C support multiple address recognition (fou r slave address with mask option) ? i 2 s C interface with external audio codec C operate as either master or slave mode C capable of handling 8-, 16-, 24- and 32-bit word sizes C mono and stereo audio data supported C i 2 s and msb justified data format supported C two 8 word fifo data buffers are provided, one for transmit and one for receive C generates interrupt requests when buffer levels cross a programmable boundary C support two dma requests, one for transmit and one for receive ? ps/2 device controller C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for data reception C s/w override bus ? ebi (external bus inte rface) support (numicro ? nuc100/nuc120 low density 64-pin package only) C accessible space: 64kb in 8-bit mode or 128kb in 16-bit mode C support 8-/16-bit data width C support byte write in 16-bit data width mode ? adc C 12-bit sar adc with 600k sps C up to 8-ch single-end input or 4-ch differential input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels C threshold voltage detection C conversion start by software programming or external input C support pdma mode ? analog comparator C up to two analog comparators C external input or internal bandgap voltage selectable at negative node C interrupt when compare result change
numicro? nuc100 product brief publication release date: may 6, 2011 - 10 - revision v2.01 C power down wake-up ? one built-in temperature sensor with 1 resolution ? brown-out detector C with 4 levels: 4.5 v/3.8 v/2.7 v/2.2 v C support brown-out interrupt and reset option ? low voltage reset C threshold voltage levels: 2.0 v ? operating temperature: -40 ~85 ? packages: C all green package (rohs) C lqfp 100-pin / 64-pin / 48-pin (100-pin for numicro ? nuc100/nuc120 medium density only)
numicro? nuc100 product brief publication release date: may 6, 2011 - 11 - revision v2.01 3 parts information list and pin configuration 3.1 numicro ? nuc100 products selection guide 3.1.1 numicro ? nuc100 medium density advance line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc100ld3an 64 kb 16 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 6 8x12-bit v - v lqfp48 nuc100le3an 128 kb 16 kb definable 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 6 8x12-bit v - v lqfp48 nuc100rd3an 64 kb 16 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 6 8x12-bit v - v lqfp64 NUC100RE3AN 128 kb 16 kb definable 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 6 8x12-bit v - v lqfp64 nuc100vd2an 64 kb 8 kb 4 kb 4 kb up to 80 4x32-bit 3 4 2 - - - 1 2 8 8x12-bit v - v lqfp100 nuc100vd3an 64 kb 16 kb 4 kb 4 kb up to 80 4x32-bit 3 4 2 - - - 1 2 8 8x12-bit v - v lqfp100 nuc100ve3an 128 kb 16 kb definable 4 kb up to 80 4x32-bit 3 4 2 - - - 1 2 8 8x12-bit v - v lqfp100 3.1.2 numicro ? nuc100 low density advance line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc100lc1bn 32 kb 4 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 4 8x12-bit v - v lqfp48 nuc100ld1bn 64 kb 4 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 4 8x12-bit v - v lqfp48 nuc100ld2bn 64 kb 8 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 4 8x12-bit v - v lqfp48 nuc100rc1bn 32 kb 4 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 4 8x12-bit v v v lqfp64 nuc100rd1bn 64 kb 4 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 4 8x12-bit v v v lqfp64 nuc100rd2bn 64 kb 8 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 4 8x12-bit v v v lqfp64
numicro? nuc100 product brief publication release date: may 6, 2011 - 12 - revision v2.01 nuc 1 0 -xx arm-based 32-bit microcontroller 0: advance line 2: usb line 3: automotive line 4: connectivity line cpu core 1: cortex-m0 5/7: arm7 9: arm9 temperature n: -40 ~ +85 e: -40 ~ +105 c: -40 ~ +125 reserve x x function 0 package type y: qfn 36 l: lqfp 48 r: lqfp 64 v: lqfp 100 x ram size 1: 4k 2: 8k 3: 16k aprom size a: 8k b: 16k c: 32k d: 64k e: 128k figure 3-1 numicro ? nuc100 series selection code
numicro? nuc100 product brief publication release date: may 6, 2011 - 13 - revision v2.01 3.2 pin configuration 3.2.1 numicro ? nuc100 medium density pin diagram 3.2.1.1 numicro ? nuc100 medium density lqfp 100 pin adc5/pa.5 adc6/pa.6 adc7/spiss21/pa.7 spiss31/int0/pb.14 cpo1/pb.13 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rxd1/pb.4 txd1/pb.5 rts1/pb.6 cts1/pb.7 ldo vdd vss cpn0/pc.7 cpp0/pc.6 cpn1/pc.15 cpp1/pc.14 int1/pb.15 xt1_out xt1_in /reset stadc/pb.8 pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 avdd vss vdd pvss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo pd.15/txd2 pd.14/rxd2 pd.7 pd.6 pb.3/cts0 pb.2/rts0 pb.1/txd0 pb.0/rxd0 pe.7 pe.8 pe.9 pe.10 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 pc.10/miso10 pc.11/mosi10 nuc100 medium density lqfp 100-pin 25 24 23 22 21 20 19 18 17 pe.15 pe.14 pe.13 spiss30/pd.8 spiclk3/pd.9 miso30/pd.10 mosi30/pd.11 miso31/pd.12 mosi31/pd.13 42 43 44 45 46 47 48 49 50 pe.11 pe.12 pc.4/miso01 pc.5/mosi01 pb.9/spiss11 pb.10/spiss01 pb.11/pwm4 pe.5/pwm5 pe.6 51 52 53 54 55 56 57 58 59 vss vdd pc.12/miso11 pc.13/mosi11 pe.0/pwm6 pe.1/pwm7 pe.2 pe.3 pe.4 84 83 82 81 80 79 78 77 76 ps2dat ps2clk spiss20/pd.0 spiclk2/pd.1 miso20/pd.2 mosi20/pd.3 miso21/pd.4 mosi21/pd.5 vref figure 3-2 numicro ? nuc100 medium density lqfp 100-pin pin diagram
numicro? nuc100 product brief publication release date: may 6, 2011 - 14 - revision v2.01 3.2.1.2 numicro ? nuc100 medium density lqfp 64 pin adc5/pa.5 adc6/pa.6 adc7/pa.7 int0/pb.14 cpo1/pb.13 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rxd1/pb.4 txd1/pb.5 rts1/pb.6 cts1/pb.7 ldo vdd vss cpn0/pc.7 cpp0/pc.6 cpn1/pc.15 cpp1/pc.14 int1/pb.15 xt1_out xt1_in /reset stadc/pb.8 pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 avdd vss vdd pvss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pc.10/miso10 pc.11/mosi10 pb.9 pb.10 pb.11/pwm4 pe.5/pwm5 pd.15/txd2 pd.14/rxd2 pd.7 pd.6 pb.3/cts0 pb.2/rts0 pb.1/txd0 pb.0/rxd0 nuc100 medium density lqfp 64-pin figure 3-3 numicro ? nuc100 medium density lqfp 64-pin pin diagram
numicro? nuc100 product brief publication release date: may 6, 2011 - 15 - revision v2.01 3.2.1.3 numicro ? nuc100 medium density lqfp 48 pin clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rxd1/pb.4 txd1/pb.5 ldo vdd vss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 figure 3-4 numicro ? nuc100 medium density lqfp 48-pin pin diagram
numicro? nuc100 product brief publication release date: may 6, 2011 - 16 - revision v2.01 3.2.2 numicro ? nuc100 low density pin diagram 3.2.2.1 numicro ? nuc100 low density lqfp 64 pin ad8/adc5/pa.5 ad7/adc6/pa.6 ad6/adc7/pa.7 ad5/cpn0/pc.7 ad4/cpp0/pc.6 ad3/cpn1/pc.15 ad2/cpp1/pc.14 int1/pb.15 xt1_out xt1_in /reset stadc/tm0/pb.8 avdd vss vdd pvss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pb.9/tm1 pb.10/tm2 pb.11/tm3 pe.5 pd.15 pd.14 pd.7 pd.6 pb.3/cts0/nwrh pb.2/rts0/nwrl pb.1/txd0 pb.0/rxd0 nuc100 low density lqfp 64-pin figure 3-5 numicro ? nuc100 low density lqfp 64-pin pin diagram
numicro? nuc100 product brief publication release date: may 6, 2011 - 17 - revision v2.01 3.2.2.2 numicro ? nuc100 low density lqfp 48 pin adc5/pa.5 adc6/pa.6 adc7/pa.7 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rxd1/pb.4 txd1/pb.5 ldo vdd vss cpn0/pc.7 cpp0/pc.6 int1/pb.15 xt1_out xt1_in /reset stadc/tm0/pb.8 pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk avdd pvss pb.9/tm1 pb.10/tm2 pb.11/tm3 pe.5 pb.3/cts0 pb.2/rts0 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 nuc100 low density lqfp 48-pin pb.1/txd0 pb.0/rxd0 pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo figure 3-6 numicro ? nuc100 low density lqfp 48-pin pin diagram
numicro? nuc100 product brief publication release date: may 6, 2011 - 18 - revision v2.01 3.3 pin description 3.3.1 numicro ? nuc100 medium density pin description 3.3.1.1 numicro ? nuc100 medium density pin description pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description 1 pe.15 i/o general purpose input/output digital pin 2 pe.14 i/o general purpose input/output digital pin 3 pe.13 i/o general purpose input/output digital pin pb.14 i/o general purpose input/output digital pin /int0 i /int0: external interrupt1 input pin 4 1 spiss31 i/o spiss31: spi3 2 nd slave select pin pb.13 i/o general purpose input/output digital pin 5 2 cpo1 o comparator1 output pin pb.12 i/o general purpose input/output digital pin cpo0 o comparator0 output pin 6 3 1 clko o frequency divider output pin 7 4 2 x32o o external 32.768 khz low speed crystal output pin 8 5 3 x32i i external 32.768 khz low speed crystal input pin pa.11 i/o general purpose input/output digital pin 9 6 4 i2c1scl i/o i2c1scl: i 2 c1 clock pin pa.10 i/o general purpose input/output digital pin 10 7 5 i2c1sda i/o i2c1sda: i 2 c1 data input/output pin pa.9 i/o general purpose input/output digital pin 11 8 6 i2c0scl i/o i2c0scl: i 2 c0 clock pin pa.8 i/o general purpose input/output digital pin 12 9 7 i2c0sda i/o i2c0sda: i 2 c0 data input/output pin pd.8 i/o general purpose input/output digital pin 13 spiss30 i/o spiss30: spi3 slave select pin pd.9 i/o general purpose input/output digital pin 14 spiclk3 i/o spiclk3: spi3 serial clock pin 15 pd.10 i/o general purpose input/output digital pin
numicro? nuc100 product brief publication release date: may 6, 2011 - 19 - revision v2.01 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description miso30 i/o miso30: spi3 miso (master in, slave out) pin pd.11 i/o general purpose input/output digital pin 16 mosi30 i/o mosi30: spi3 mosi (master out, slave in) pin pd.12 i/o general purpose input/output digital pin 17 miso31 i/o miso31: spi3 2 nd miso (master in, slave out) pin pd.13 i/o general purpose input/output digital pin 18 mosi31 i/o mosi31: spi3 2 nd mosi (master out, slave in) pin pb.4 i/o general purpose input/output digital pin 19 10 8 rxd1 i rxd1: data receiver input pin for uart1 pb.5 i/o general purpose input/output digital pin 20 11 9 txd1 o txd1: data transmitter output pin for uart1 pb.6 i/o general purpose input/output digital pin 21 12 rts1 o rts1: request to send output pin for uart1 pb.7 i/o general purpose input/output digital pin 22 13 cts1 i cts1: clear to send input pin for uart1 23 14 10 ldo p ldo output pin 24 15 11 vdd p power supply for i/o ports and ldo source for internal pll and digital function 25 16 12 vss p ground 26 pe.12 i/o general purpose input/output digital pin 27 pe.11 i/o general purpose input/output digital pin 28 pe.10 i/o general purpose input/output digital pin 29 pe.9 i/o general purpose input/output digital pin 30 pe.8 i/o general purpose input/output digital pin 31 pe.7 i/o general purpose input/output digital pin pb.0 i/o general purpose input/output digital pin 32 17 13 rxd0 i rxd0: data receiver input pin for uart0 pb.1 i/o general purpose input/output digital pin 33 18 14 txd0 o txd0: data transmitter output pin for uart0 34 19 15 pb.2 i/o general purpose input/output digital pin
numicro? nuc100 product brief publication release date: may 6, 2011 - 20 - revision v2.01 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description rts0 o rts0: request to send output pin for uart0 pb.3 i/o general purpose input/output digital pin 35 20 16 cts0 i cts0: clear to send input pin for uart0 36 21 pd.6 i/o general purpose input/output digital pin 37 22 pd.7 i/o general purpose input/output digital pin pd.14 i/o general purpose input/output digital pin 38 23 rxd2 i rxd2: data receiver input pin for uart2 pd.15 i/o general purpose input/output digital pin 39 24 txd2 o txd2: data transmitter output pin for uart2 pc.5 i/o general purpose input/output digital pin 40 mosi01 i/o mosi01: spi0 2 nd mosi (master out, slave in) pin pc.4 i/o general purpose input/output digital pin 41 miso01 i/o miso01: spi0 2 nd miso (master in, slave out) pin pc.3 i/o general purpose input/output digital pin mosi00 i/o mosi00: spi0 mosi (master out, slave in) pin 42 25 17 i2sdo o i2sdo: i 2 s data output pc.2 i/o general purpose input/output digital pin miso00 i/o miso00: spi0 miso (master in, slave out) pin 43 26 18 i2sdi i i2sdi: i 2 s data input pc.1 i/o general purpose input/output digital pin spiclk0 i/o spiclk0: spi0 serial clock pin 44 27 19 i2sbclk i/o i2sbclk: i 2 s bit clock pin pc.0 i/o general purpose input/output digital pin spiss00 i/o spiss00: spi0 slave select pin 45 28 20 i2slrcl k i/o i2slrclk: i 2 s left right channel clock 46 pe.6 i/o general purpose input/output digital pin pe.5 i/o general purpose input/output digital pin 47 29 21 pwm5 i/o pwm5: pwm output/capture input 48 30 22 pb.11 i/o general purpose input/output digital pin
numicro? nuc100 product brief publication release date: may 6, 2011 - 21 - revision v2.01 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pwm4 i/o pwm4: pwm output/capture input 31 23 pb.10 i/o general purpose input/output digital pin 49 spiss01 i/o spiss01: spi0 2 nd slave select pin 32 24 pb.9 i/o general purpose input/output digital pin 50 spiss11 i/o spiss11: spi1 2 nd slave select pin 51 pe.4 i/o general purpose input/output digital pin 52 pe.3 i/o general purpose input/output digital pin 53 pe.2 i/o general purpose input/output digital pin pe.1 i/o general purpose input/output digital pin 54 pwm7 i/o pwm7: pwm output/capture input pe.0 i/o general purpose input/output digital pin 55 pwm6 i/o pwm6: pwm output/capture input pc.13 i/o general purpose input/output digital pin 56 mosi11 i/o mosi11: spi1 2 nd mosi (master out, slave in) pin pc.12 i/o general purpose input/output digital pin 57 miso11 i/o miso11: spi1 2 nd miso (master in, slave out) pin pc.11 i/o general purpose input/output digital pin 58 33 mosi10 i/o mosi10: spi1 mosi (master out, slave in) pin pc.10 i/o general purpose input/output digital pin 59 34 miso10 i/o miso10: spi1 miso (master in, slave out) pin pc.9 i/o general purpose input/output digital pin 60 35 spiclk1 i/o spiclk1: spi1 serial clock pin pc.8 i/o general purpose input/output digital pin 61 36 spiss10 i/o spiss10: spi1 slave select pin pa.15 i/o general purpose input/output digital pin pwm3 i/o pwm3: pwm output/capture input 62 37 25 i2smclk o i2smclk: i 2 s master clock output pin pa.14 i/o general purpose input/output digital pin 63 38 26 pwm2 i/o pwm2: pwm output/capture input
numicro? nuc100 product brief publication release date: may 6, 2011 - 22 - revision v2.01 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pa.13 i/o general purpose input/output digital pin 64 39 27 pwm1 i/o pwm1: pwm output/capture input pa.12 i/o general purpose input/output digital pin 65 40 28 pwm0 i/o pwm0: pwm output/capture input 66 41 29 ice_dat i/o serial wired debugger data pin 67 42 30 ice_ck i serial wired debugger clock pin 68 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 69 vss p ground 70 43 31 avss ap ground pin for analog circuit pa.0 i/o general purpose input/output digital pin 71 44 32 adc0 ai adc0: adc analog input pa.1 i/o general purpose input/output digital pin 72 45 33 adc1 ai adc1: adc analog input pa.2 i/o general purpose input/output digital pin 73 46 34 adc2 ai adc2: adc analog input pa.3 i/o general purpose input/output digital pin 74 47 35 adc3 ai adc3: adc analog input pa.4 i/o general purpose input/output digital pin 75 48 36 adc4 ai adc4: adc analog input pa.5 i/o general purpose input/output digital pin 76 49 37 adc5 ai adc5: adc analog input pa.6 i/o general purpose input/output digital pin 77 50 38 adc6 ai adc6: adc analog input pa.7 i/o general purpose input/output digital pin 51 39 adc7 ai adc7: adc analog input 78 spiss21 i/o spiss21: spi2 2 nd slave select pin 79 vref ap voltage reference input for adc 80 52 40 avdd ap power supply for internal analog circuit 81 pd.0 i/o general purpose input/output digital pin
numicro? nuc100 product brief publication release date: may 6, 2011 - 23 - revision v2.01 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description spiss20 i/o spiss20: spi2 slave select pin pd.1 i/o general purpose input/output digital pin 82 spiclk2 i/o spiclk2: spi2 serial clock pin pd.2 i/o general purpose input/output digital pin 83 miso20 i/o miso20: spi2 miso (master in, slave out) pin pd.3 i/o general purpose input/output digital pin 84 mosi20 i/o mosi20: spi2 mosi (master out, slave in) pin pd.4 i/o general purpose input/output digital pin 85 miso21 i/o miso21: spi2 2 nd miso (master in, slave out) pin pd.5 i/o general purpose input/output digital pin 86 mosi21 i/o mosi21: spi2 2 nd mosi (master out, slave in) pin pc.7 i/o general purpose input/output digital pin 87 53 41 cpn0 ai cpn0: comparator0 negative input pin pc.6 i/o general purpose input/output digital pin 88 54 42 cpp0 ai cpp0: comparator0 positive input pin pc.15 i/o general purpose input/output digital pin 89 55 cpn1 ai cpn1: comparator1 negative input pin pc.14 i/o general purpose input/output digital pin 90 56 cpp1 ai cpp1: comparator1 positive input pin pb.15 i/o general purpose input/output digital pin 91 57 43 /int1 i /int1: external interrupt0 input pin 92 58 44 xt1_out o external 4~24 mhz high speed crystal output pin 93 59 45 xt1_in i external 4~24 mhz high speed crystal input pin 94 60 46 /reset i external reset input: low active, set this pin low reset chip to initial stat e. with internal pull-up. 95 61 vss p ground 96 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 97 ps2dat i/o ps/2 data pin 98 ps2clk i/o ps/2 clock pin 99 63 47 pvss p pll ground
numicro? nuc100 product brief publication release date: may 6, 2011 - 24 - revision v2.01 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pb.8 i/o general purpose input/output digital pin 100 64 48 stadc i stadc: adc external trigger input. note: pin type i=digital input, o=digital outpu t; ai=analog input; p=power pin; ap=analog power
numicro? nuc100 product brief publication release date: may 6, 2011 - 25 - revision v2.01 3.3.2 numicro ? nuc100 low density pin description 3.3.2.1 numicro ? nuc100 low density pin description pin no. lqfp 64 lqfp 48 pin name pin type description pb.14 i/o general purpose input/output digital pin 1 /int0 i /int0: external interrupt1 input pin pb.13 i/o general purpose input/output digital pin cpo1 o comparator1 output pin 2 ad1 i/o ebi address/data bus bit1 (64pin package only) pb.12 i/o general purpose input/output digital pin cpo0 o comparator0 output pin 1 clko o frequency divider output pin 3 ad0 i/o ebi address/data bus bit0 (64pin package only) 4 2 x32o o external 32.768 khz low speed crystal output pin 5 3 x32i i external 32.768 khz low speed crystal input pin pa.11 i/o general purpose input/output digital pin 4 i2c1scl i/o i2c1scl: i 2 c1 clock pin 6 nrd o ebi read enable output pin (64pin package only) pa.10 i/o general purpose input/output digital pin 5 i2c1sda i/o i2c1sda: i 2 c1 data input/output pin 7 nwr o ebi write enable output pin (64pin package only) pa.9 i/o general purpose input/output digital pin 8 6 i2c0scl i/o i2c0scl: i 2 c0 clock pin pa.8 i/o general purpose input/output digital pin 9 7 i2c0sda i/o i2c0sda: i 2 c0 data input/output pin pb.4 i/o general purpose input/output digital pin 10 8 rxd1 i rxd1: data receiver input pin for uart1 pb.5 i/o general purpose input/output digital pin 11 9 txd1 o txd1: data transmitter output pin for uart1 pb.6 i/o general purpose input/output digital pin 12 rts1 o rts1: request to send output pin for uart1
numicro? nuc100 product brief publication release date: may 6, 2011 - 26 - revision v2.01 pin no. lqfp 64 lqfp 48 pin name pin type description ale o ebi address latch enable output pin (64pin package only) pb.7 i/o general purpose input/output digital pin cts1 i cts1: clear to send input pin for uart1 13 ncs o ebi chip select enable output pin (64pin package only) 14 10 ldo p ldo output pin 15 11 vdd p power supply for i/o ports and ldo source for internal pll and digital function 16 12 vss p ground pb.0 i/o general purpose input/output digital pin 17 13 rxd0 i rxd0: data receiver input pin for uart0 pb.1 i/o general purpose input/output digital pin 18 14 txd0 o txd0: data transmitter output pin for uart0 pb.2 i/o general purpose input/output digital pin 15 rts0 o rts0: request to send output pin for uart0 19 nwrl o ebi low byte write enable output pin (64pin package only) pb.3 i/o general purpose input/output digital pin 16 cts0 i cts0: clear to send input pin for uart0 20 nwrh o ebi high byte write enable output pin (64pin package only) 21 pd.6 i/o general purpose input/output digital pin 22 pd.7 i/o general purpose input/output digital pin 23 pd.14 i/o general purpose input/output digital pin 24 pd.15 i/o general purpose input/output digital pin pc.3 i/o general purpose input/output digital pin mosi00 i/o mosi00: spi0 mosi (master out, slave in) pin 25 17 i2sdo o i2sdo: i 2 s data output pc.2 i/o general purpose input/output digital pin miso00 i/o miso00: spi0 miso (master in, slave out) pin 26 18 i2sdi i i2sdi: i 2 s data input
numicro? nuc100 product brief publication release date: may 6, 2011 - 27 - revision v2.01 pin no. lqfp 64 lqfp 48 pin name pin type description pc.1 i/o general purpose input/output digital pin spiclk0 i/o spiclk0: spi0 serial clock pin 27 19 i2sbclk i/o i2sbclk: i 2 s bit clock pin pc.0 i/o general purpose input/output digital pin spiss00 i/o spiss00: spi0 slave select pin 28 20 i2slrclk i/o i2slrclk: i 2 s left right channel clock 29 21 pe.5 i/o general purpose input/output digital pin pb.11 i/o general purpose input/output digital pin 30 22 tm3 i/o tm3: timer3 event count er input / toggle output pb.10 i/o general purpose input/output digital pin 31 23 tm2 i/o tm2: timer2 event count er input / toggle output pb.9 i/o general purpose input/output digital pin 32 24 tm1 i/o tm1: timer1 event count er input / toggle output pc.11 i/o general purpose input/output digital pin 33 mosi10 i/o mosi10: spi1 mosi (master out, slave in) pin pc.10 i/o general purpose input/output digital pin 34 miso10 i/o miso10: spi1 miso (master in, slave out) pin pc.9 i/o general purpose input/output digital pin 35 spiclk1 i/o spiclk1: spi1 serial clock pin pc.8 i/o general purpose input/output digital pin spiss10 i/o spiss10: spi1 slave select pin 36 mclk o ebi external clock output pin (64pin package only) pa.15 i/o general purpose input/output digital pin pwm3 i/o pwm3: pwm output/capture input 37 25 i2smclk o i2smclk: i 2 s master clock output pin pa.14 i/o general purpose input/output digital pin 26 pwm2 i/o pwm2: pwm output/capture input 38 ad15 i/o ebi address/data bus bit15 (64pin package only) pa.13 i/o general purpose input/output digital pin 39 27 pwm1 i/o pwm1: pwm output/capture input
numicro? nuc100 product brief publication release date: may 6, 2011 - 28 - revision v2.01 pin no. lqfp 64 lqfp 48 pin name pin type description ad14 i/o ebi address/data bus bit14 (64pin package only) pa.12 i/o general purpose input/output digital pin 28 pwm0 i/o pwm0: pwm output/capture input 40 ad13 i/o ebi address/data bus bit13 (64pin package only) 41 29 ice_dat i/o serial wired debugger data pin 42 30 ice_ck i serial wired debugger clock pin 43 31 avss ap ground pin for analog circuit pa.0 i/o general purpose input/output digital pin 44 32 adc0 ai adc0: adc analog input pa.1 i/o general purpose input/output digital pin 33 adc1 ai adc1: adc analog input 45 ad12 i/o ebi address/data bus bit12 (64pin package only) pa.2 i/o general purpose input/output digital pin 34 adc2 ai adc2: adc analog input 46 ad11 i/o ebi address/data bus bit11 (64pin package only) pa.3 i/o general purpose input/output digital pin 35 adc3 ai adc3: adc analog input 47 ad10 i/o ebi address/data bus bit10 (64pin package only) pa.4 i/o general purpose input/output digital pin 36 adc4 ai adc4: adc analog input 48 ad9 i/o ebi address/data bus bit9 (64pin package only) pa.5 i/o general purpose input/output digital pin 37 adc5 ai adc5: adc analog input 49 ad8 i/o ebi address/data bus bit8 (64pin package only) pa.6 i/o general purpose input/output digital pin 38 adc6 ai adc6: adc analog input 50 ad7 i/o ebi address/data bus bit7 (64pin package only) pa.7 i/o general purpose input/output digital pin 39 adc7 ai adc7: adc analog input 51 ad6 i/o ebi address/data bus bit6 (64pin package only)
numicro? nuc100 product brief publication release date: may 6, 2011 - 29 - revision v2.01 pin no. lqfp 64 lqfp 48 pin name pin type description 52 40 avdd ap power supply for internal analog circuit pc.7 i/o general purpose input/output digital pin 41 cpn0 ai cpn0: comparator0 negative input pin 53 ad5 i/o ebi address/data bus bit5 (64pin package only) pc.6 i/o general purpose input/output digital pin 42 cpp0 ai cpp0: comparator0 positive input pin 54 ad4 i/o ebi address/data bus bit4 (64pin package only) pc.15 i/o general purpose input/output digital pin cpn1 ai cpn1: comparator1 negative input pin 55 ad3 i/o ebi address/data bus bit3 (64pin package only) pc.14 i/o general purpose input/output digital pin cpp1 ai cpp1: comparator1 positive input pin 56 ad2 i/o ebi address/data bus bit2 (64pin package only) pb.15 i/o general purpose input/output digital pin 57 43 /int1 i /int1: external interrupt0 input pin 58 44 xt1_out o external 4~24 mhz high speed crystal output pin 59 45 xt1_in i external 4~24 mhz high speed crystal input pin 60 46 /reset i external reset input: low active, set this pin low reset chip to initial stat e. with internal pull-up. 61 vss p ground 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 63 47 pvss p pll ground pb.8 i/o general purpose input/output digital pin stadc i stadc: adc external trigger input. 64 48 tm0 i/o tm0: timer0 event count er input / toggle output note: pin type i=digital input, o=digital outpu t; ai=analog input; p=power pin; ap=analog power
numicro? nuc100 product brief publication release date: may 6, 2011 - 30 - revision v2.01 4 block diagram 4.1 numicro ? nuc100 medium density block diagram flash 128kb cortex-m0 50mhz clk_ctl pdma isp 4kb sram 16kb gpio a,b,c,d,e uart 1 -115k i2c 1 timer 2/3 rtc wdt i2c 0 spi 0/1 uart 0 -3m pwm 0~3 timer 0/1/ 12-bit adc analog comparator por brown-out lvr peripherals with pdma i2s 10 khz 32.768 khz p l l 22.1184 mhz 4~24 mhz ldo 2.5v~ 5.5v pwm 4~7 uart 2 -115k spi 2/3 ps2 figure 4-1 numicro ? nuc100 medium density block diagram
numicro? nuc100 product brief publication release date: may 6, 2011 - 31 - revision v2.01 4.2 numicro ? nu c100 low density block diagram flash 64kb cortex-m0 50mhz clk_ctl pdma isp 4kb sram 8kb gpio a,b,c,d,e uart 1 -115k i2c 1 timer 2/3 rtc wdt i2c 0 spi 0/1 uart 0 -3m pwm 0~3 timer 0/1/ 12-bit adc analog comparator por brown-out lvr peripherals with pdma i2s p l l ldo 2.5v~ 5.5v 10 khz 32.768 khz 22.1184 mhz 4~24 mhz figure 4-2 numicro ? nuc100 low density block diagram 5 electrical characteristics 5.1 absolute maximum ratings symbol parameter min max unit dc power supply vdd? vss -0.3 +7.0 v input voltage vin vss-0.3 vdd+0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature ta -40 +85 c storage temperature tst -55 +150 c maximum current into vdd - 120 ma maximum current out of vss 120 ma maximum current sunk by a i/o pin 35 ma
numicro? nuc100 product brief publication release date: may 6, 2011 - 32 - revision v2.01 maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions beyond thos e listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
numicro? nuc100 product brief publication release date: may 6, 2011 - 33 - revision v2.01 5.2 dc electrical characteristics 5.2.1 numicro ? nuc100/nuc120 medium density dc electrical characteristics (vdd-vss=3.3 v, ta = 25 c, fosc = 50 mhz unless otherwise specified.) specification parameter sym. min. typ. max. unit test conditions operation voltage v dd 2.5 5.5 v v dd =2.5 v ~ 5.5 v up to 50 mhz power ground v ss av ss -0.3 v ldo output voltage v ldo -10% 2.5 +10% v v dd > 2.7 v analog operating voltage av dd 0 v dd v analog reference voltage vref 0 av dd v i dd1 54 ma v dd = 5.5 v@50 mhz, enable all ip and pll, xtal=12 mhz i dd2 31 ma v dd = 5.5 v@ 50 mhz, disable all ip and enable pll, xtal=12 mhz i dd3 51 ma v dd = 3 v@50 mhz, enable all ip and pll, xtal=12 mhz operating current normal run mode @ 50 mhz i dd4 28 ma v dd = 3 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i dd5 22 ma v dd = 5.5 v@12 mhz, enable all ip and disable pll, xtal=12 mhz i dd6 14 ma v dd = 5.5 v@12 mhz, disable all ip and disable pll, xtal=12 mhz operating current normal run mode @ 12 mhz i dd7 20 ma v dd = 3 v@12mhz, enable all ip and disable pll, xtal=12 mhz
numicro? nuc100 product brief publication release date: may 6, 2011 - 34 - revision v2.01 specification parameter sym. min. typ. max. unit test conditions i dd8 12 ma v dd = 3 v@12 mhz, disable all ip and disable pll, xtal=12 mhz i dd9 15 ma v dd = 5 v@4 mhz, enable all ip and disable pll, xtal=4 mhz i dd10 11 ma v dd = 5 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i dd11 13 ma v dd = 3 v@4 mhz, enable all ip and disable pll, xtal=4 mhz operating current normal run mode @ 4 mhz i dd12 9 ma v dd = 3 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i idle1 38 ma v dd = 5.5 v@50 mhz, enable all ip and pll, xtal=12 mhz i idle2 15 ma vdd=5.5 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i idle3 35 ma v dd = 3 v@50 mhz, enable all ip and pll, xtal=12 mhz operating current idle mode @ 50 mhz i idle4 13 ma v dd = 3 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i idle5 13 ma v dd = 5.5 v@12 mhz, enable all ip and disable pll, xtal=12 mhz i idle6 5.5 ma v dd = 5.5 v@12 mhz, disable all ip and disable pll, xtal=12 mhz operating current idle mode @ 12 mhz i idle7 12 ma v dd = 3 v@12 mhz, enable all ip and disable pll, xtal=12 mhz
numicro? nuc100 product brief publication release date: may 6, 2011 - 35 - revision v2.01 specification parameter sym. min. typ. max. unit test conditions i idle8 4 ma v dd = 3 v@12 mhz, disable all ip and disable pll, xtal=12 mhz i idle9 8.5 ma v dd = 5 v@4 mhz, enable all ip and disable pll, xtal=4 mhz i idle10 3.5 ma v dd = 5 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i idle11 7 ma v dd = 3 v@4 mhz, enable all ip and disable pll, xtal=4 mhz operating current idle mode @ 4 mhz i idle12 2.5 ma v dd = 3 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i pwd1 23 a v dd = 5.5 v, rtc off, no load @ disable bov function i pwd2 18 a v dd = 3.3 v, rtc off, no load @ disable bov function i pwd3 28 a v dd = 5.5 v, rtc run , no load @ disable bov function standby current power down mode i pwd4 22 a v dd = 3.3 v, rtc run , no load @ disable bov function input current pa, pb, pc, pd, pe (quasi-bidirectional mode) i in1 -50 -60 a v dd = 5.5 v, v in = 0 v or v in =v dd input current at /reset [1] i in2 -55 -45 -30 a v dd = 3.3 v, v in = 0.45 v input leakage current pa, pb, pc, pd, pe i lk -2 - +2 a v dd = 5.5 v, 0 numicro? nuc100 product brief publication release date: may 6, 2011 - 36 - revision v2.01 specification parameter sym. min. typ. max. unit test conditions input high voltage pa, pb, pc, pd, pe (schmitt input) v ih2 0.2 v dd v hysteresis voltage of pa~pe (schmitt input) v hy 0.2 v dd v 0 - 0.8 v dd = 4.5 v input low voltage xt1 [*2] v il3 0 - 0.4 v v dd = 3.0 v 3.5 - v dd +0.2 v v dd = 5.5 v input high voltage xt1 [*2] v ih3 2.4 - v dd +0.2 v dd = 3.0 v input low voltage x32i [*2] v il4 0 - 0.4 v input high voltage x32i [*2] v ih4 1.7 2.5 v negative going threshold (schmitt input), /reset v ils -0.5 - 0.3 v dd v positive going threshold (schmitt input), /reset v ihs 0.7 v dd - v dd +0.5 v i sr11 -300 -370 -450 a v dd = 4.5 v, v s = 2.4 v i sr12 -50 -70 -90 a v dd = 2.7 v, v s = 2.2 v source current pa, pb, pc, pd, pe (quasi-bidirectional mode) i sr12 -40 -60 -80 a v dd = 2.5 v, v s = 2.0 v i sr21 -20 -24 -28 ma v dd = 4.5 v, v s = 2.4 v i sr22 -4 -6 -8 ma v dd = 2.7 v, v s = 2.2 v source current pa, pb, pc, pd, pe (push-pull mode) i sr22 -3 -5 -7 ma v dd = 2.5 v, v s = 2.0 v i sk1 10 16 20 ma v dd = 4.5 v, v s = 0.45 v i sk1 7 10 13 ma v dd = 2.7 v, v s = 0.45 v sink current pa, pb, pc, pd, pe (quasi-bidirectional and push-pull mode) i sk1 6 9 12 ma v dd = 2.5 v, v s = 0.45 v brown-out voltage with bov_vl [1:0] =00b v bo2.2 2.1 2.2 2.3 v brown-out voltage with bov_vl [1:0] =01b v bo2.7 2.6 2.7 2.8 v brown-out voltage with bov_vl [1:0] =10b v bo3.8 3.7 3.8 3.9 v brown-out voltage with bov_vl [1:0] =11b v bo4.5 4.4 4.5 4.6 v hysteresis range of bod voltage v bh 30 - 150 mv v dd = 2.5 v~5.5 v note:
numicro? nuc100 product brief publication release date: may 6, 2011 - 37 - revision v2.01 1. /reset pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. pins of pa, pb, pc, pd and pe can source a transition current when they are being externally driven from 1 to 0. in the condition of v dd =5.5 v, 5he transition current reaches its maximum value when v in approximates to 2 v.
numicro? nuc100 product brief publication release date: may 6, 2011 - 38 - revision v2.01 5.2.2 numicro ? nuc100/nuc120 low density dc electrical characteristics (vdd-vss=3.3 v, ta = 25 c, fosc = 50 mhz unless otherwise specified.) specification parameter sym. min. typ. max. unit test conditions operation voltage v dd 2.5 5.5 v v dd =2.5 v ~ 5.5 v up to 50 mhz power ground v ss av ss -0.3 v ldo output voltage v ldo -10% 2.5 +10% v v dd > 2.7 v analog operating voltage av dd 0 v dd v analog reference voltage vref 0 av dd v i dd1 46 ma v dd = 5.5 v@50 mhz, enable all ip and pll, xtal=12 mhz i dd2 30 ma v dd = 5.5 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i dd3 44 ma v dd = 3 v@50 mhz, enable all ip and pll, xtal=12 mhz operating current normal run mode @ 50 mhz i dd4 28 ma v dd = 3 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i dd5 19 ma v dd = 5.5 v@12 mhz, enable all ip and disable pll, xtal=12 mhz i dd6 13 ma v dd = 5.5 v@12 mhz, disable all ip and disable pll, xtal=12 mhz i dd7 17 ma v dd = 3 v@12 mhz, enable all ip and disable pll, xtal=12 mhz operating current normal run mode @ 12 mhz i dd8 11.5 ma v dd = 3 v@12 mhz, disable all ip and disable pll, xtal=12 mhz
numicro? nuc100 product brief publication release date: may 6, 2011 - 39 - revision v2.01 specification parameter sym. min. typ. max. unit test conditions i dd9 13.5 ma v dd = 5 v@4 mhz, enable all ip and disable pll, xtal=4 mhz i dd10 10 ma v dd = 5 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i dd11 12 ma v dd = 3 v@4 mhz, enable all ip and disable pll, xtal=4 mhz operating current normal run mode @ 4 mhz i dd12 8 ma v dd = 3 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i idle1 30 ma v dd = 5.5 v@50 mhz, enable all ip and pll, xtal=12 mhz i idle2 13 ma vdd=5.5 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i idle3 28 ma v dd = 3 v@50 mhz, enable all ip and pll, xtal=12 mhz operating current idle mode @ 50 mhz i idle4 12 ma v dd = 3 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i idle5 11 ma v dd = 5.5 v@12 mhz, enable all ip and disable pll, xtal=12 mhz i idle6 5 ma v dd = 5.5 v@12 mhz, disable all ip and disable pll, xtal=12 mhz i idle7 10 ma v dd = 3 v@12 mhz, enable all ip and disable pll, xtal=12 mhz operating current idle mode @ 12 mhz i idle8 4 ma v dd = 3 v@12 mhz, disable all ip and disable pll, xtal=12 mhz
numicro? nuc100 product brief publication release date: may 6, 2011 - 40 - revision v2.01 specification parameter sym. min. typ. max. unit test conditions i idle9 7 ma v dd = 5 v@4 mhz, enable all ip and disable pll, xtal=4 mhz i idle10 3.5 ma v dd = 5 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i idle11 6 ma v dd = 3 v@4 mhz, enable all ip and disable pll, xtal=4 mhz operating current idle mode @ 4 mhz i idle12 2.5 ma v dd = 3 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i pwd1 17 a v dd = 5.5 v, rtc off, no load @ disable bov function i pwd2 14.5 a v dd = 3.3 v, rtc off, no load @ disable bov function i pwd3 20 a v dd = 5.5 v, rtc run , no load @ disable bov function standby current power down mode i pwd4 17 a v dd = 3.3 v, rtc run , no load @ disable bov function input current pa, pb, pc, pd, pe (quasi-bidirectional mode) i in1 -50 -60 a v dd = 5.5 v, v in = 0 v or v in =v dd input current at /reset [1] i in2 -55 -45 -30 a v dd = 3.3 v, v in = 0.45 v input leakage current pa, pb, pc, pd, pe i lk -2 - +2 a v dd = 5.5 v, 0 numicro? nuc100 product brief publication release date: may 6, 2011 - 41 - revision v2.01 specification parameter sym. min. typ. max. unit test conditions 0 - 0.4 v dd = 3.0 v 3.5 - v dd +0.2 v v dd = 5.5 v input high voltage xt1 [*2] v ih3 2.4 - v dd +0.2 v dd = 3.0 v input low voltage x32i [*2] v il4 0 - 0.4 v input high voltage x32i [*2] v ih4 1.7 2.5 v negative going threshold (schmitt input), /reset v ils -0.5 - 0.3 v dd v positive going threshold (schmitt input), /reset v ihs 0.7 v dd - v dd +0.5 v i sr11 -300 -370 -450 a v dd = 4.5 v, v s = 2.4 v i sr12 -50 -70 -90 a v dd = 2.7 v, v s = 2.2 v source current pa, pb, pc, pd, pe (quasi-bidirectional mode) i sr12 -40 -60 -80 a v dd = 2.5 v, v s = 2.0 v i sr21 -20 -24 -28 ma v dd = 4.5 v, v s = 2.4 v i sr22 -4 -6 -8 ma v dd = 2.7 v, v s = 2.2 v source current pa, pb, pc, pd, pe (push-pull mode) i sr22 -3 -5 -7 ma v dd = 2.5 v, v s = 2.0 v i sk1 10 16 20 ma v dd = 4.5 v, v s = 0.45 v i sk1 7 10 13 ma v dd = 2.7 v, v s = 0.45 v sink current pa, pb, pc, pd, pe (quasi-bidirectional and push-pull mode) i sk1 6 9 12 ma v dd = 2.5 v, v s = 0.45 v brown-out voltage with bov_vl [1:0] =00b v bo2.2 2.1 2.2 2.3 v brown-out voltage with bov_vl [1:0] =01b v bo2.7 2.6 2.7 2.8 v brown-out voltage with bov_vl [1:0] =10b v bo3.8 3.7 3.8 3.9 v brown-out voltage with bov_vl [1:0] =11b v bo4.5 4.4 4.5 4.6 v hysteresis range of bod voltage v bh 30 - 150 mv v dd = 2.5 v~5.5 v note: 1. /reset pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. pins of pa, pb, pc, pd and pe can source a transition current when they are being externally driven from 1 to 0. in the condition of v dd =5.5 v, 5he transition current reaches its maximum value when v in approximates to 2 v.
numicro? nuc100 product brief publication release date: may 6, 2011 - 42 - revision v2.01 5.2.3 operating current curve (test condition: run nop) 1. xtal clock = 12 mhz, pll disable, all-ip disable: unit: ma 2. xtal clock = 12 mhz, pll disable, all-ip enable unit: ma
numicro? nuc100 product brief publication release date: may 6, 2011 - 43 - revision v2.01 3. xtal clock = 12 mhz, pll enable, all-ip disable unit: ma 4. xtal clock = 12 mhz, pll enable, all-ip enable unit: ma
numicro? nuc100 product brief publication release date: may 6, 2011 - 44 - revision v2.01 5.2.4 idle current curve 1. xtal clock = 12 mhz, pll disable, all-ip disable unit: ma 2. xtal clock = 12 mhz, pll disable, all-ip enable unit: ma
numicro? nuc100 product brief publication release date: may 6, 2011 - 45 - revision v2.01 3. xtal clock = 12 mhz, pll enable, all-ip disable unit: ma 4. xtal clock = 12 mhz, pll enable, all-ip enable unit: ma
numicro? nuc100 product brief publication release date: may 6, 2011 - 46 - revision v2.01 5.2.5 power down current curve xtal clock = 12 mhz, pll disable unit: ma
numicro? nuc100 product brief publication release date: may 6, 2011 - 47 - revision v2.01 5.3 ac electrical characteristics t clcl t clcx t chcx t clch t chcl note: duty cycle is 50%. symbol parameter condition min. typ. max. unit t chcx clock high time 20 - - ns t clcx clock low time 20 - - ns t clch clock rise time - - 10 ns t chcl clock fall time - - 10 ns 5.3.1 external 4~24 mhz high speed crystal parameter condition min. typ. max. unit input clock frequency external crystal 4 12 24 mhz temperature - -40 - 85 vdd - 2.5 5 5.5 v 5.3.1.1 typical crystal application circuits crystal c1 c2 r 4 mhz ~ 24 mhz without without without figure 5-1 typical crystal application circuit
numicro? nuc100 product brief publication release date: may 6, 2011 - 48 - revision v2.01 5.3.2 external 32.768 khz low speed crystal parameter condition min. typ. max. unit input clock frequency external crystal - 32.768 - khz temperature - -40 - 85 vdd - 2.5 - 5.5 v 5.3.3 internal 22.1184 mhz high speed oscillator parameter condition min. typ. max. unit supply voltage [1] - 2.5 - 5.5 v center frequency - - 22.1184 - mhz +25 ; v dd =5 v -1 - +1 % calibrated internal oscillator frequency -40 ~+85 ; vdd=2.5 v~5.5 v -3 - +3 % operation current v dd =5 v - 500 - ua 5.3.4 internal 10 khz low speed oscillator parameter condition min. typ. max. unit supply voltage [1] - 2.5 - 5.5 v center frequency - - 10 - khz +25 ; v dd =5 v -30 - +30 % calibrated internal oscillator frequency -40 ~+85 ; v dd =2.5 v~5.5 v -50 - +50 % note: internal operation voltage comes from ldo.
numicro? nuc100 product brief publication release date: may 6, 2011 - 49 - revision v2.01 5.4 analog characteristics 5.4.1 specification of 12-bit saradc symbol parameter min. typ. max. unit - resolution - - 12 bit dnl differential nonlinearity error - 3 - lsb inl integral nonlinearity error - 4 - lsb eo offset error - 1 10 lsb eg gain error (transfer gain) - 1 1.005 - - monotonic guaranteed fadc adc clock frequency - - 16 mhz tcal calibration time - 127 - clock ts sample time - 7 - clock tadc conversion time - 13 - clock fs sample rate - - 600 k sps vldo - 2.5 - v vadd supply voltage 3 - 5.5 v idd - 0.5 - ma idda supply current (avg.) - 1.5 - ma vref reference voltage - vdda - v irefp reference current (avg.) - 1 - ma vin reference voltage 0 - vref v cin capacitance - 5 - pf
numicro? nuc100 product brief publication release date: may 6, 2011 - 50 - revision v2.01 5.4.2 specification of ldo & power management parameter min. typ. max. unit note input voltage 2.7 5 5.5 v v dd input voltage output voltage -10% 2.5 +10% v v dd > 2.7 v temperature -40 25 85 quiescent current (pd=0) - 100 - ua quiescent current (pd=1) - 5 - ua iload (pd=0) - - 100 ma iload (pd=1) - - 100 ua cbp - 10 - uf resr=1ohm note: 1. it is recommended that a 10uf or higher capacitor and a 100nf bypass capacitor are connected between vdd and the closest vss pin of the device. 2. for ensuring power stability, a 10uf or higher capacitor must be connected between ldo pin and the closest vss pin of the device.
numicro? nuc100 product brief publication release date: may 6, 2011 - 51 - revision v2.01 5.4.3 specification of low voltage reset parameter condition min. typ. max. unit operation voltage - 1.7 - 5.5 v quiescent current vdd5v=5.5 v - - 5 ua temperature - -40 25 85 temperature=25 1.7 2.0 2.3 v temperature=-40 - 2.4 - v threshold voltage temperature=85 - 1.6 - v hysteresis - 0 0 0 v 5.4.4 specification of brown-out detector parameter condition min. typ. max. unit operation voltage - 2.5 - 5.5 v quiescent current avdd=5.5 v - - 125 a temperature - -40 25 85 bov_vl[1:0]=11 4.4 4.5 4.6 v bov_vl [1:0]=10 3.7 3.8 3.9 v bov_vl [1:0]=01 2.6 2.7 2.8 v brown-out voltage bov_vl [1:0]=00 2.1 2.2 2.3 v hysteresis - 30 - 150 mv 5.4.5 specification of power-on reset (5 v) parameter condition min. typ. max. unit temperature - -40 25 85 reset voltage v+ - 2 - v quiescent current vin>reset voltage - 1 - na
numicro? nuc100 product brief publication release date: may 6, 2011 - 52 - revision v2.01 5.4.6 specification of temperature sensor parameter conditions min. typ. max. unit supply voltage [1] 2.5 - 5.5 v temperature -40 - 125 current consumption 6.4 - 10.5 ua gain -1.95 -2 -2.05 mv/ offset temp=0 688 708 730 mv note: internal operation voltage comes form ldo. 5.4.7 specification of comparator parameter condition min. typ. max. unit temperature - -40 25 85 vdd - 2.4 3 5.5 v vdd current 20 ua@vdd=3 v - 20 40 ua input offset voltage - - 5 15 mv output swing - 0.1 - vdd-0.1 v input common mode range - 0.1 - vdd-1.2 v dc gain - - 70 - db propagation delay @vcm=1.2 v & vdiff=0.1 v - 200 - ns comparison voltage 20 mv@vcm=1 v 50 mv@vcm=0.1 v 50 mv@vcm=vdd-1.2 @10 mv for non- hysteresis 10 20 - mv hysteresis one bit control w/o & w. hysteresis @vcm=0.4 v ~ vdd-1.2 v - 10 - mv wake-up time @cinp=1.3 v cinn=1.2 v - - 2 us
numicro? nuc100 product brief publication release date: may 6, 2011 - 53 - revision v2.01 5.4.8 specification of usb phy 5.4.8.1 usb dc electrical characteristics symbol parameter conditions min. typ. max. unit v ih input high (driven) 2.0 v v il input low 0.8 v v di differential input sensitivity |padp-padm| 0.2 v v cm differential common-mode range includes v di range 0.8 2.5 v v se single-ended receiver threshold 0.8 2.0 v receiver hysteresis 200 mv v ol output low (driven) 0 0.3 v v oh output high (driven) 2.8 3.6 v v crs output signal cross voltage 1.3 2.0 v r pu pull-up resistor 1.425 1.575 k ? r pd pull-down resistor 14.25 15.75 k ? v trm termination voltage for upstream port pull up (rpu) 3.0 3.6 v z drv driver output resistance steady state drive* 10 ? c in transceiver capacitance pin to gnd 20 pf *driver output resistance doesn?t in clude series resistor resistance. 5.4.8.2 usb full-speed driver electrical characteristics symbol parameter conditions min. typ. max. unit t fr rise time c l =50p 4 20 ns t ff fall time c l =50p 4 20 ns t frff rise and fall time matching t frff =t fr /t ff 90 111.11 % 5.4.8.3 usb power dissipation symbol parameter conditions min. typ. max. unit standby 50 ua input mode ua i vddreg (full speed) vddd and vddreg supply current (steady state) output mode ua
numicro? nuc100 product brief publication release date: may 6, 2011 - 54 - revision v2.01 5.5 spi dynamic characteristics symbol parameter min. typ. max. unit spi master mode (vdd = 4.5v ~ 5.5v, 30pf loading capacitor) t ds data setup time 26 18 - ns t dh data hold time 0 - - ns t v data output valid time - 4 6 ns spi master mode (vdd = 3.0v ~ 3.6v, 30pf loading capacitor) t ds data setup time 39 26 - ns t dh data hold time 0 - - ns t v data output valid time - 6 10 ns spi slave mode (vdd = 4.5v ~ 5.5v, 30pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+4 - - ns t v data output valid time - 2*pclk+19 2*pclk+27 ns spi slave mode (vdd = 3.0v ~ 3.6v, 30pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+8 - - ns t v data output valid time - 2*pclk+27 2*pclk+40 ns
numicro? nuc100 product brief publication release date: may 6, 2011 - 55 - revision v2.01 figure 5.5-1 spi master dynamic characteristics timing figure 5.5-2 spi slave dynamic characteristics timing
numicro? nuc100 product brief publication release date: may 6, 2011 - 56 - revision v2.01 6 package dimensions 6.1 100l lqfp (14x14x1.4 mm footprint 2.0mm) controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 0.638 0.630 0.622 0.50 14.10 0.20 0.27 1.45 1.60 14.00 1.40 13.90 0.10 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.055 0.020 0.556 0.551 0.547 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y a1 a 2 l1 e 0.009 0.006 0.15 0.22 7 13.90 14.00 14.10 15.80 16.00 16.20 15.80 16.00 16.20 0.556 0.551 0.547 0.638 0.630 0.622 d d e e b a2 a1 a l1 e c l y h h 1 100 25 26 50 51 7 7
numicro? nuc100 product brief publication release date: may 6, 2011 - 57 - revision v2.01 6.2 64l lqfp (10x10x1.4mm footprint 2.0 mm) 0 7 0 1.00 0.75 0.60 12.00 0.45 0.039 0.030 0.024 0.472 0.018 0.50 0.20 0.27 1.45 1.60 10.00 1.40 0.09 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.393 0.055 0.020 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.20 7 0.393 10.00 0.472 12.00 0.006 0.15 0.004 0.10 3.5 3.5
numicro? nuc100 product brief publication release date: may 6, 2011 - 58 - revision v2.01 6.3 48l lqfp (7x7x1.4mm footprint 2.0mm)
numicro? nuc100 product brief publication release date: may 6, 2011 - 59 - revision v2.01 7 revision history version date page/ chap. description v1.12 april 9, 2010 - initial issued v1.13 may 31, 2010 4.2 add operati on current of dc characteristics v1.14 aug. 23, 2010 4.2 modify oper ation current of dc characteristics v2.00 nov. 11, 2010 - update low density and selection table v2.01 may 6, 2011 - remove nuc130/nuc140 add spi dynamic characteristics remove tm0~3 of medium density remove word ?microwire? in all document
numicro? nuc100 product brief publication release date: may 6, 2011 - 60 - revision v2.01 important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, ?insecure usage?. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for ve hicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customer?s risk, and in the event that third parties lay claims to nuvoton as a result of customer?s insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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